1. Field of Invention
The present invention relates to technology for an amplifier circuit used in the receiver of a wireless communication device such as a cell phone or PHS phone, and relates more particularly to an amplifier circuit and a wireless communication device.
2. Description of Related Art
A variable gain amplifier according to the prior art is shown in FIG. 11. In FIG. 11 a high frequency signal S201 is input to a current conversion circuit 200 through an input node 201. The high frequency signal S201 is input to the base of a transistor 203, and a signal current I202 corresponding to the high frequency signal S201 is then output through the collector of the transistor 203 from the output node 202 of the current conversion circuit 200.
The signal current I202 is then input to a gain control circuit 204 connected in common to the output node 202. The gain control circuit 204 consists of transistors 205 and 206 having the emitters connected in common. The gain control circuit 204 selectively outputs the signal current I202 to the collectors 230, 231 of the transistors 205 and 206, respectively, based on the voltage S207, S208 applied to the bases 207, 208 of the transistors 205 and 206.
The collector 231 of transistor 206 is connected to the main load impedance 215 of the amplifier circuit and to node 210 of the impedance circuit 209, and outputs gain signal S231. The collector 230 of transistor 205 is connected to node 211 of the impedance circuit 209, and outputs gain signal S230.
The impedance circuit 209 has three nodes, node 210, node 211, and a power supply node 290 connected to the power supply. An impedance device 212 with a prescribed impedance is connected between node 210 and node 211, and another impedance device 213 with a prescribed impedance is connected between node 211 and the power supply node 290. The impedance between node 210 and the power supply node 290 is greater than the impedance between node 211 and the power supply node 290 by the impedance of impedance device 212. The load circuit 214 is electrically coupled through matching device 216 to the output pin 217 for impedance matching with the output pin 217.
In the high gain mode the base voltage S208 of the transistor 206 is set high relative to the base voltage S207 of transistor 205 so that transistor 205 is off and transistor 206 is on. All of signal current I202 is converted at this time to the signal current I231 flowing to the collector 231 of transistor 206. The total load of this signal current I231 is determined by the parallel connection of load impedance 215 with the impedance of the impedance circuit 209 measured from node 210. The signal current I231 is converted to the gain signal S231 at collector 231 by the impedance of the total load thus determined, and is output through matching device 216 to the output pin 217 as the output signal S217.
The gain signal S231 can be expressed in terms of the signal current I231, the impedance R212 and R213 of impedance devices 212 and 213, and the impedance Z215 of load impedance 215 as follows where A//B=A*B/(A+B).
                              S          ⁢                                          ⁢          231                =                ⁢                  I          ⁢                                          ⁢          206          *                      (                                          Z                ⁢                                                                  ⁢                215                            //                              (                                                      R                    ⁢                                                                                  ⁢                    212                                    +                                      R                    ⁢                                                                                  ⁢                    213                                                  )                                      )                                                  =                ⁢                  I          ⁢                                          ⁢          231          *          Z          ⁢                                          ⁢          215          *                                    (                                                R                  ⁢                                                                          ⁢                  212                                +                                  R                  ⁢                                                                          ⁢                  213                                            )                        /                          (                                                Z                  ⁢                                                                          ⁢                  215                                +                                  R                  ⁢                                                                          ⁢                  212                                +                                  R                  ⁢                                                                          ⁢                  213                                            )                                          
In the low gain mode the base voltage S207 of transistor 205 is set higher than the base voltage S208 of transistor 206 so that transistor 206 is off and transistor 205 is on. The signal current I202 is converted to the signal current I230 flowing to the collector 230 of the transistor 205. The total load of this signal current I230 is determined by the parallel connection of impedance device 213 with the serially connected load impedance 215 and impedance device 212. The signal current I230 is converted to the gain signal S230 at collector 230 by the impedance of the total load thus determined, and is output through impedance device 212 and matching device 216 to the output pin 217 as the output signal S217.
The gain signal S230 can be expressed as follows using the signal current I230, impedances R212 and R213, and impedance Z215.
                                                        S              ⁢                                                          ⁢              230                        =                        ⁢                          I              ⁢                                                          ⁢              230              *                              (                                                      (                                                                  Z                        ⁢                                                                                                  ⁢                        215                                            +                                              R                        ⁢                                                                                                  ⁢                        212                                                              )                                    //                                      R                    ⁢                                                                                  ⁢                    213                                                  )                                              )                *        Z        ⁢                                  ⁢                  215          /                      (                                          R                ⁢                                                                  ⁢                212                            +                              Z                ⁢                                                                  ⁢                215                                      )                                                  =                ⁢                  I          ⁢                                          ⁢          230          *          Z          ⁢                                          ⁢          215          *          R          ⁢                                          ⁢                      213            /                          (                                                Z                  ⁢                                                                          ⁢                  215                                +                                  R                  ⁢                                                                          ⁢                  212                                +                                  R                  ⁢                                                                          ⁢                  213                                            )                                          
If the characteristics of transistors 205 and 206 are the same, signal current I230 and signal current I231 will be equal, and the relationship between gain signal S230 and gain signal S231 will be as follows.S230=S231*R213/(R212+R213)
In other words, the gain signal S230 in the low gain mode is determined by the impedance ratio between impedances R212 and R213.
See, for example, U.S. Pat. No. 5,999,056 (corresponding to Japanese Laid-open Patent Publication No. 2005-519920).
A first problem with the prior art described above is that gain drops in the high gain mode. Conventionally, the amplifier load is preferably determined only by the main load impedance 215, but the total load impedance is reduced by connecting impedance circuit 209 in parallel, and gain therefore drops in the high gain mode. An arrangement that increases current consumption could be used to compensate for this drop, but increasing the current consumption must be avoided in portable devices that are powered by a battery.
A second problem with the prior art is that is a drop in the distortion characteristic of the low gain mode apparent at the third order input intercept point (IIP3) or the 1-dB compression point (P1 dB). This is because the voltage S230 at node 211 of the impedance circuit 209 drops, and the collector-emitter voltage of transistor 205 drops with the dc current flow to the amplifier circuit.
One way to solve the first problem is to increase the total impedance of the impedance circuit 209 and suppress the impedance loss from the parallel connection of the load impedance 215, but this has the side effect of lowering the voltage S230 at node 211 of the impedance circuit 209 and degrading the distortion characteristic.
Another potential solution is to lower the impedance of the impedance device 213 to a level that the voltage drop of the node 211 can be ignored, and increase the impedance of the impedance device 212 to increase the total impedance of the impedance circuit 209. In this case, however, the ratio (R213/(R212+R213)) of the impedance devices 212 and 213 cannot be set above a constant value, and the gain of the low gain mode therefore cannot be set as desired.
One way to solve the second problem is to lower the total impedance of the impedance circuit 209, but this has the side effect of lowering the gain of the high gain mode. This also conflicts with the solution to the first problem.
Solutions to the foregoing first and second problems are thus a trade-off, and cannot be simultaneously solved.